Semiconductor device structures including a rectilinear array of openings

ABSTRACT

A method of forming an array of openings in a substrate. The method comprises forming a template structure comprising a plurality of parallel features and a plurality of additional parallel features perpendicularly intersecting the plurality of additional parallel features of the plurality over a substrate to define wells, each of the plurality of parallel features having substantially the same dimensions and relative spacing as each of the plurality of additional parallel features. A block copolymer material is formed in each of the wells. The block copolymer material is processed to form a patterned polymer material defining a pattern of openings. The pattern of openings is transferred to the substrate to form an array of openings in the substrate. A method of forming a semiconductor device structure, and a semiconductor device structure are also described.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No. 13/646,131, filed Oct. 5, 2012, pending, the disclosure of which is hereby incorporated herein in its entirety by this reference.

TECHNICAL FIELD

Embodiments of the disclosure relate to the field of semiconductor device design and fabrication. More specifically, embodiments of the disclosure relate to methods of forming an array of openings in a substrate, to related methods of forming a semiconductor device structure, and to a related semiconductor device structure.

BACKGROUND

A continuing goal of integrated circuit fabrication is to decrease the dimensions thereof. Integrated circuit dimensions can be decreased by reducing the dimensions and spacing of the constituent features or structures thereof. For example, by decreasing the dimensions and spacing of features (e.g., storage capacitors, access transistors, access lines, etc.) of a memory device, the overall dimensions of the memory device may be decreased while maintaining or increasing the storage capacity of the memory device.

Reducing the dimensions and spacing of semiconductor device features places ever increasing demands on the methods used to form the features. For example, due to limitations imposed by optics and radiation wavelengths, many conventional photolithographic methods cannot facilitate the formation of features having critical dimensions (e.g., widths, diameters, etc.) of less than about sixty (60) nanometers (nm). Electron beam (E-beam) lithography and extreme ultraviolet (EUV) lithography have been used to form features having critical dimensions less than 60 nm, but generally require complex processes and significant costs.

One approach for achieving features having critical dimensions of less than about 60 nm has been the use of pitch density multiplication processes, such as pitch density doubling processes. In a conventional pitch density doubling process, a photolithographic process is used to form photoresist lines over a sacrificial material over a substrate. The sacrificial material is etched using the photoresist lines to form mandrels, the photoresist lines are removed, spacers are formed on sides of the mandrels, and the mandrels are removed. The remaining spacers are used as a mask to pattern the substrate. Where the initial photolithography process formed one feature and one trench across a particular width of the substrate, after pitch density doubling, the same width of the substrate can include two smaller features and two smaller trenches, the width of each of the smaller trenches defined by the width of the spacers. Thus, the use of pitch density doubling can halve the minimum critical dimensions of features formed by the photolithographic processes, resulting in features having minimum critical dimension of about 30 nm. However, to achieve features having critical dimensions less than about 30 nm, the pitch density doubling process needs to be repeated (i.e., the process becomes a pitch density quadrupling process), significantly increasing processing time as well as energy and material costs.

Another approach for achieving semiconductor device features having critical dimensions of less than about 60 nm has been the use of self-assembling (SA) block copolymers. For example, an SA block copolymer deposited within a trench having particular graphoepitaxial characteristics (e.g., dimensions, wetting properties, etc.) may be annealed to form select morphology (e.g., spherical, lamellar, cylindrical, etc.) domains of one polymer block of the SA block copolymer within a matrix domain of another polymer block of the SA block copolymer. The select morphology domains or the matrix domain can be selectively removed, and the remaining select morphology domains or matrix domain utilized as an etch mask for patterning features into an underlying substrate. As the dimensions of the select morphology domains and the matrix domain are at least partially determined by the chain length of the SA block copolymer, feature dimensions much smaller than 60 nm are achievable (e.g., dimensions similar to those achievable through E-beam and EUV lithography processes). Such methods have, for example, been used to form close-packed, hexagonal arrays of openings in an underlying substrate. However, certain semiconductor device structures may utilize different (i.e., non-hexagonal) array configurations. For example, Dynamic Random Access Memory (DRAM) device structures may utilize rectilinear arrays of openings (e.g., contact openings) rather than hexagonal arrays of openings.

A need, therefore, exists for new, simple, and cost-efficient methods of forming a rectilinear array of openings for a semiconductor device structure, such as, for example, a rectilinear contact array for a memory device structure, that enables the formation of the closely packed openings having critical dimensions (e.g., widths, diameters, etc.) less than or equal to about 30 nm.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 13B are cross-sectional (i.e., FIGS. 1 through 7A, 8A, 9A, 10A, 11A, 12A, and 13A) and top-down (FIGS. 7B, 8B, 9B, 10B, 11B, 12B, and 13B) views of a semiconductor device structure in accordance with embodiments of the disclosure, and illustrate a method of forming a rectilinear array of openings in a substrate of a semiconductor device structure, in accordance with embodiments of the disclosure.

DETAILED DESCRIPTION

Methods of forming a rectilinear array of openings (e.g., a rectilinear contact array) in a substrate are disclosed, as are related methods of forming a semiconductor device structure including the rectilinear array of openings, and a related semiconductor device structure including the rectilinear array of openings. In some embodiments, a template structure having the dimensions, spacing, and wetting characteristics for forming a rectilinear array of cylindrical domains of a first polymer within a matrix domain of a second polymer from a block copolymer material may be formed over a substrate by way of pitch density doubling processes. An appropriate block copolymer material may be deposited in wells defined by the template structure, the block polymer material may be processed (e.g., annealed) to form a self-assembled block copolymer material, and the cylindrical domains of the first polymer may be selectively removed to form a patterned polymer material. The patterned polymer material may be used as a mask to form a rectilinear array of openings in the substrate. The openings of the rectilinear array may each have substantially the same width, such as less than or equal to about 30 nm, and a pitch between adjacent openings may be substantially uniform, such as less than or equal to about 50 nm. The rectilinear array of openings may, for example, be utilized in a dynamic random access memory (DRAM) device. The methods of forming the rectilinear array of openings disclosed herein may decrease processing complexity, steps, and cost relative to conventional methods of forming a rectilinear array of openings. The methods of the disclosure may enable increased opening density, facilitating increased performance in semiconductor device structures (e.g., DRAM cells) and semiconductor devices (e.g., DRAM devices) that rely on high opening (e.g., contact) density.

As used herein, the term “rectilinear array” means and includes an array including rows of features that intersect columns of features at about a ninety degree (90°) angle. Accordingly, a “rectilinear array of openings” means and includes an array of openings including rows of openings that intersect columns of openings at about a ninety degree (90°) angle.

As used herein, the term “pitch” refers to the distance between identical points in two adjacent (i.e., neighboring) features. By way of non-limiting example, the pitch between two adjacent cylindrical domains may be viewed as the sum of the radii of the adjacent cylindrical domains and any space between the adjacent cylindrical domains. Stated another way, the pitch in the foregoing example may be characterized as the distance between the centers of the adjacent cylindrical domains.

As used herein, relational terms, such as “first,” “second,” “over,” “top,” “bottom,” “underlying,” etc., are used for clarity and convenience in understanding the disclosure and accompanying drawings and does not connote or depend on any specific preference, orientation, or order, except where the context clearly indicates otherwise.

As used herein, the term “substantially,” in reference to a given parameter, property, or condition, means to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a small degree of variance, such as within acceptable manufacturing tolerances.

The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art will understand that the embodiments of the present disclosure may be practiced without employing these specific details. Indeed, the embodiments of the present disclosure may be practiced in conjunction with conventional fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a semiconductor device. The semiconductor device structures described below do not form a complete semiconductor device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form the complete semiconductor device from the semiconductor device structures may be performed by conventional fabrication techniques. Also note, any drawings accompanying the present application are for illustrative purposes only, and are thus not drawn to scale. Additionally, elements common between figures may retain the same numerical designation.

FIGS. 1 through 13B, are simplified cross-sectional (i.e., FIGS. 1 through 7A, 8A, 9A, 10A, 11A, 12A, and 13A) and top-down (i.e., FIGS. 7B, 8B, 9B, 10B, 11B, 12B, and 13B) views illustrating embodiments of a method of forming a rectilinear array of openings in a substrate of a semiconductor device structure, such as a rectilinear contact array for a DRAM device structure. With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods described herein may be used in various devices. In other words, the methods of the disclosure may be used whenever it is desired to form a rectilinear array of openings in a substrate.

Referring to FIG. 1, a semiconductor device structure 100 may include a substrate 102, a substrate masking material 104 over the substrate 102, a template material 106 over the substrate masking material 104, template masking materials 108 over the template material 106, and a patterned photoresist material 114 over the template masking materials 108. As used herein, the term “substrate” means and includes a base material or other construction upon which additional materials are formed. The substrate 102 may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode or a semiconductor substrate having one or more layers, structures or regions formed thereon. The substrate 102 may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (SOI) substrates, such as silicon-on-sapphire (SOS) substrates and silicon-on-glass (SOG) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate 102 may be doped or undoped.

The substrate masking material 104 may be a material that is selectively etchable relative to a domain of a self-assembled block copolymer material to be formed over the substrate masking material 104, as described in further detail below. As used herein, a material is “selectively etchable” relative to another material if the material exhibits an etch rate that is at least about five times (5×) greater than the etch rate of another material, such as about ten times (10×) greater, about twenty times (20×) greater, or about forty times (40×) greater. The substrate 102 may be selectively etchable relative to the substrate masking material 104. In some embodiments, the substrate masking material 104 is formed of and includes amorphous carbon. A thickness of the substrate masking material 104 may be selected at least partially based on the etch chemistries and process conditions used to form the rectilinear array of openings of the disclosure, as described in further detail below. By way of non-limiting example, the substrate masking material 104 may have a thickness within a range of from about 100 nanometers (nm) to about 1000 nm, such as from about 200 nm to about 800 nm, or from about 300 nm to about 700 nm. In some embodiments, the substrate masking material 104 has a thickness of about 600 nm.

The template material 106 may be a material that, upon being patterned, facilitates forming a self-assembled block copolymer material including a rectilinear array of cylindrical domains of a first polymer within a matrix domain of a second polymer, as described in further detail below. The template material 106 may, for example, be a material that is preferential wetting to a polymer block (e.g., a minority block, or a majority block) of the block copolymer material (as well as any homopolymers included in the block copolymer material that are of the same polymer type as the polymer block). As a non-limiting example, template material 106 may be formed of and include at least one of a silicon oxide, a silicon nitride, a silicon oxycarbide, and a dielectric anti-reflective coating (DARC) (e.g., a silicon oxynitride, such as a silicon-rich silicon oxynitride). In some embodiments, the template material 106 is selected to be preferential wetting toward a polymethylmethacrylate (PMMA) block of poly(styrene-b-methylmethacrylate) (PS-b-PMMA). In additional embodiments, the template material 106 is selected to be preferential wetting toward a polydimethylsiloxane (PDMS) block of poly(styrene-block-dimethylsiloxane) (PS-b-PDMS). The template material 106 may have a thickness T₁ conducive to the patterning of the template material 106 to form a template structure, as described in further detail below. By way of non-limiting example, the thickness T₁ of the template material 106 may be within a range of from about 50 nanometers (nm) to about 500 nm, such as from about 50 nm to about 100 nm. In some embodiments, the thickness T₁ of the template material 106 is about 75 nm.

The template masking materials 108 may include materials that aid in the patterning of the template material 106. For example, as depicted in FIG. 1, the template masking materials 108 may include a protective material 110 over the template material 106 and a hard mask material 112 over the protective material 110. Each of the protective material 110 and the hard mask material 112 may be selectively etchable relative to spacers to be formed over the template masking materials 108. The protective material 110 and the hard mask material 112 may be the same as or different than the substrate masking material 104 and the template material 106, respectively. By way of non-limiting example, the protective material 110 may be formed of and include amorphous carbon, and the hard mask material 112 may be formed of and include at least one of silicon, a silicon oxide, a silicon nitride, a silicon oxycarbide, aluminum oxide, and a silicon oxynitride. The protective material 110 may have a thickness within a range of from about 50 nm to about 300 nm, such as from about 60 nm to about 200 nm. The hard mask material 112 may have a thickness within a range of from about 10 nm to about 50 nm, such as from about 10 nm to about 40 nm. In some embodiments, the protective material 110 has a thickness of about 70 nm, and the hard mask material 112 has a thickness of about 26 nm. In embodiments where the template material 106 is selectively etchable relative to a spacer material to be formed thereover, at least a portion of the template masking materials 108 (e.g., at least one of the protective material 110 and the hard mask material 112) may, optionally, be omitted.

Each of the substrate 102, the substrate masking material 104, the template material 106, and the template masking materials 108 (if present) may be formed using conventional processes including, but not limited to, physical vapor deposition (“PVD”), chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), or spin-coating. PVD includes, but is not limited to, sputtering, evaporation, or ionized PVD. Such processes are known in the art and, therefore, are not described in detail herein.

The patterned photoresist material 114 may include parallel photoresist lines 116 separated by first trenches 118. As used herein, the term “parallel” means substantially parallel. Each of the parallel photoresist lines 116 may be formed of and include a conventional photoresist, such as a photoresist compatible with 13.7 nm, 157 nm, 193 nm, 248 nm, or 365 nm wavelength systems, a photoresist compatible with 193 nm wavelength immersion systems, or a photoresist compatible with electron beam lithographic systems. By way of non-limiting example, each of the parallel photoresist lines 116 may be formed of and include an argon fluoride (ArF) sensitive photoresist (i.e., a photoresist suitable for use with an ArF light source), or a krypton fluoride (KrF) sensitive photoresist (i.e., a photoresist suitable for use with a KrF light source).

Each of the parallel photoresist lines 116 may have substantially the same width W₁, thickness T₂, and length (not shown). In addition, the parallel photoresist lines 116 may be regularly spaced by a distance D₁ (i.e., the width of each of the first trenches 118). Accordingly, a pitch P₁ between centerlines C₁ of adjacent parallel photoresist lines may be substantially uniform throughout the patterned photoresist material 114. The dimensions and spacing of the parallel photoresist lines 116 may be selected to provide desired dimensions and spacing to parallel spacers to be formed on the parallel photoresist lines 116. For example, the width W₁, and the centerline C₁ location of each of the parallel photoresist lines 116 may be selected to facilitate the formation of parallel spacers exhibiting smaller dimensions and decreased pitch relative to the parallel photoresist lines 116, as described in further detail below. In some embodiments, the width W₁ of each of the parallel photoresist lines 116 is about 50 nm, the distance D₁ between adjacent parallel photoresist lines is about 70 nm, and the pitch P₁ between adjacent parallel photoresist lines is about 120 nm.

The patterned photoresist material 114 may be formed using conventional processing techniques, which are not described in detail herein. By way of non-limiting example, a photoresist material (not shown) may be formed over the template masking materials 108 and exposed to an appropriate wavelength of radiation through a reticle (not shown) and then developed. The parallel photoresist lines 116 may correlate to portions of the photoresist material remaining after the development, and the first trenches 118 may correlate to portions of the photoresist material removed during the development.

Referring to next to FIG. 2, the patterned photoresist material 114 (FIG. 1) may be used to form a patterned spacer material 120 including parallel spacers 122 separated by second trenches 124. The patterned spacer material 120 may define a first pattern 126 to be transferred to the template material 106, as described in further detail below. Each of the parallel spacers 122 may be formed of and include a material suitable for use as a mask for selectively removing (e.g., etching) of portions of the template masking materials 108 and the template material 106. By way of non-limiting example, each of the parallel spacers 122 may be formed of and include a silicon oxide or a silicon nitride. In some embodiments, each of the parallel spacers 122 is formed of and includes a silicon oxide.

Each of the parallel spacers 122 may have substantially the same width W₂, thickness T₃, and length (not shown). The thickness T₃ of each of the parallel spacers 122 may be substantially the same as the thickness T₂ of each of the parallel photoresist lines 116 (FIG. 1). In addition, the parallel spacers 122 may be oriented parallel to one another, and may be regularly spaced by a distance D₂ (i.e., the width of each of the second trenches 124) that is substantially the same as the width W₁ of each of the parallel photoresist lines 116. A pitch P₂ between centerlines C₂ of adjacent parallel spacers may be equal to about half of the pitch P₁ between the centerlines C₁ of adjacent photoresist lines of the patterned photoresist material 114 (FIG. 1). The dimensions and spacing of the parallel spacers 122 may be selected to provide desired dimensions and spacing for features of a template structure to be formed using the patterned spacer material 120, as described in further detail below. The width W₂ of each of the parallel spacers 122 may be within a range of from about 20 percent to about 40 percent of a target (e.g., desired) pitch between adjacent openings of a rectilinear array of openings to be formed using the template structure, such as from about 20 percent to about 30 percent of the target pitch. The distance D₂ between each of the parallel spacers 122 may be within a range of from about 180 percent to about 160 percent of the target pitch between adjacent openings of the rectilinear array of openings to be formed, such as from about 180 percent to about 170 percent of the target pitch. The pitch P₂ between adjacent parallel spacers of the patterned spacer material 120 may be about two times (2×) the target pitch between adjacent openings of the rectilinear array of openings to be formed.

By way of non-limiting example, if a target pitch between adjacent openings of the rectilinear array of openings to be formed is about 30 nm, the width W₂ of each of the parallel spacers 122 may be within a range of from about 6 nm to about 12 nm, the distance D₂ between adjacent parallel spacers of the patterned spacer material 120 may be within a range of from about 54 nm and about 48 nm, and the pitch P₂ between centerlines C₂ of adjacent parallel spacers of the patterned spacer material 120 may be about 60 nm. In some embodiments, the width W₂ of each of the parallel spacers 122 is about 10 nm, the distance D₂ between adjacent parallel spacers of the patterned spacer material 120 is about 50 nm, and the pitch P₂ between adjacent parallel spacers of the patterned spacer material 120 is about 60 nm.

A pitch density doubling process may be utilized to form the patterned spacer material 120 using the patterned photoresist material 114. For example, referring collectively to FIGS. 1 and 2, a spacer material (not shown) may be conformally formed (e.g., deposited using a PVD process, a CVD process, an ALD process, or a spin-coating process) over exposed surfaces of the parallel photoresist lines 116 and the template masking materials 108. A thickness of the spacer material may correspond to the width W₂ of the parallel spacers 122 to be formed. An anisotropic etching process may be performed to remove the spacer material from horizontal surfaces of the parallel photoresist lines 116 and the template masking materials 108, while maintaining the spacer material on vertical surfaces of the parallel photoresist lines 116. As used herein, each of the terms “horizontal” and “lateral” means and includes extending in a direction substantially parallel to the substrate 102, regardless of the orientation of the substrate 102. Accordingly, as used herein, each of the terms “vertical” and “longitudinal” means and includes extending in a direction substantially perpendicular to the substrate 102, regardless of the orientation of the substrate 102. The parallel photoresist lines 116 may then be removed (e.g., etched, such as dry etched with a silicon-dioxide-containing plasma), resulting in the patterned spacer material 120.

In additional embodiments, the patterned spacer material 120 may be formed using structures other than the parallel photoresist lines 116 of the patterned photoresist material 114. Such structures may, for example, be utilized if forming the spacer material over exposed surfaces of the parallel photoresist lines 116 would damage or degrade (e.g., thermally degrade) the parallel photoresist lines 116. By way of non-limiting example, a pattern defined by the patterned photoresist material 114 may be transferred (e.g., by way of at least one etching process) to the template masking materials 108 to form a patterned template masking material (not shown). The patterned spacer material 120 may then be formed using the patterned template masking material through a process substantially similar to that described above in relation to forming the patterned spacer material 120 using the patterned photoresist material 114.

Referring to FIG. 3, the first pattern 126 defined by the patterned spacer material 120 may be transferred or extended into the template material 106 (FIG. 2) to form an intermediate template structure 128 including parallel features 130 protruding from a base 132. The parallel features 130 may have substantially the same width W₂, length (not shown), and pitch P₂ as each of the parallel spacers 122. A height H₁ of each of the parallel features 130 may be within a range of from about 55 percent to about 45 percent of the thickness T₁ of the template material 106. A height H₂ of the base 132 may be equal to the difference between the height H₁ of each of the parallel features 130 and the thickness T₁ of the template material 106. In some embodiments, the width W₂ of each of the parallel features 130 is about 10 nm, the pitch P₂ between adjacent parallel features is about 60 nm, the height H₁ of each of the parallel features 130 is about 35 nm, and the height H₂ of the base 132 is about 40 nm.

To form the intermediate template structure 128, the parallel spacers 122 of the patterned spacer material 120 may be used as a mask for at least one etching process (e.g., an anisotropic etching process) to substantially remove unmasked portions (i.e., portions not underlying the parallel spacers 122) of each of the template masking materials 108 and the template material 106. The unmasked portions of the template masking materials 108 may be completely removed, and the unmasked portions of the template material 106 may be partially removed. The etching process may, for example, extend the first pattern 126 from about 45 percent to about 55 percent of the way through the template material 106. As a non-limiting example, if the thickness T₁ of the template material 106 is about 75 nm, the first pattern 126 may be extended from about 35 nm to about 40 nm into the template material 106.

Following the formation of the intermediate template structure 128, remaining portions of the parallel spacers 122 and the template masking materials 108 may be removed, as depicted in FIG. 4. The remaining portions of the parallel spacers 122 and the template masking materials 108 may be removed using conventional processes, such as conventional etching processes, which are not described in detail herein.

Referring to FIG. 5, which illustrates a cross-sectional view of the semiconductor device structure 100 taken from a viewpoint approximately 90 degrees clockwise of that of FIGS. 1 through 4, additional template masking materials 134 may be formed over the intermediate template structure 128, and another patterned photoresist material 140 may be formed over the additional template masking materials 134. In FIG. 5, the base 132 of the intermediate template structure 128 is shown, but the parallel features 130 are not illustrated because they are covered by the additional template masking materials 134. The additional template masking materials 134 may include materials that aid in further patterning the intermediate template structure 128 (FIG. 4). For example, the additional template masking materials 134 may include an additional protective material 136 over the intermediate template structure 128, and an additional hard mask material 138 over the additional protective material 136. Each of the additional protective material 136 and the additional hard mask material 138 may be selectively etchable relative to additional parallel spacers to be formed over the additional template masking materials 134. The additional protective material 136 and the additional hard mask material 138 may be the same as or different than the protective material 110 and the hard mask material 112 previously described with reference to FIG. 1, respectively. By way of non-limiting example, the additional protective material 136 may be formed of and include amorphous carbon, and the additional hard mask material 138 may be formed of and include at least one of silicon, a silicon oxide, a silicon nitride, a silicon oxycarbide, aluminum oxide, and a silicon oxynitride.

The additional protective material 136 may have a thickness sufficient to cover and surround each of the parallel features 130 (FIG. 4) of the intermediate template structure 128, such as a thickness within a range of from about 40 nm to about 80 nm, or from about 50 nm to about 60 nm. The additional hard mask material 138 may have a thickness within a range of from about 10 nm to about 50 nm, such as from about 10 nm to about 40 nm. In some embodiments, the additional hard mask material 138 has a thickness of about 80 nm, and the additional hard mask material 138 has a thickness of about 26 nm. In embodiments where the intermediate template structure 128 is selectively etchable relative to an additional spacer material to be formed thereover, at least a portion of the additional template masking materials 134 (e.g., the additional hard mask material 138) may, optionally, be omitted. The additional template masking materials 134 may be formed using conventional processes (e.g., CVD, PVD, ALD, or spin-coating), which are not described in detail herein.

The another patterned photoresist material 140 may include additional parallel photoresist lines 142 separated by third trenches 144. The additional parallel photoresist lines 142 may be formed of and include a conventional photoresist (e.g., an ArF sensitive photoresist, a KrF sensitive photoresist, etc.) that is the same as or different than that of the parallel photoresist lines 116 of the patterned photoresist material 114, previously described with respect to FIG. 1. The additional parallel photoresist lines 142 may have substantially similar dimensions and spacing as the parallel photoresist lines 116, except oriented in a direction substantially perpendicular to that of the parallel features 130 (FIG. 4) of the intermediate template structure 128 (i.e., perpendicular to the direction of the parallel photoresist lines 116). For example, each of the additional parallel photoresist lines 142 may have a width W₃, thickness T₄, and length (not shown) substantially the same as the width W₁, the thickness T₂, and the length (not shown) of the parallel photoresist lines 116, respectively. In additional embodiments, at least one of the thickness T₄ and the length of each of the additional parallel photoresist lines 142 may be different than at least one of the thickness T₂ and the length of the parallel photoresist lines 116. The additional parallel photoresist lines 142 may be regularly spaced by a distance D₃ that is substantially the same as the distance D₁ between each of the parallel photoresist lines 116. A pitch P₃ between centerlines C₃ of adjacent photoresist lines of the another patterned photoresist material 140 may be substantially the same as the pitch P₁ between the centerlines C₁ of the adjacent photoresist lines of the patterned photoresist material 114. In some embodiments, the width W₃ of each of the additional parallel photoresist lines 142 is about 50 nm, the distance D₃ between adjacent additional parallel photoresist lines is about 70 nm, and the pitch P₃ between the centerlines C₃ of adjacent additional parallel photoresist lines is about 120 nm. The another patterned photoresist material 140 may be formed using conventional processes, such as those previously described in relation to forming the patterned photoresist material 114.

Referring to next to FIG. 6, the another patterned photoresist material 140 (FIG. 5) may be used to form another patterned spacer material 146 including additional parallel spacers 148 separated by fourth trenches 150. The another patterned spacer material 146 may define a second pattern 152 to be transferred to the intermediate template structure 128 (FIG. 4), as described in further detail below. Each of the additional parallel spacers 148 may be formed of and include a material suitable for use as a mask for selectively removing (e.g., etching) portions of the additional template masking materials 134 and the intermediate template structure 128. The material of the additional parallel spacers 148 may be the same as or different than the material of the parallel spacers 122 of the patterned spacer material 120, previously described with respect to FIG. 2. In some embodiments, each of the additional parallel spacers 148 is formed of and includes a silicon oxide.

The dimensions and spacing of the additional parallel spacers 148 may be selected to provide desired dimensions and spacing for features of a template structure to be formed using the another patterned spacer material 146, as described in further detail below. The additional parallel spacers 148 may have substantially similar dimensions and spacing as the parallel spacers 122 of the patterned spacer material 120, except oriented in a direction substantially perpendicular to that of the parallel features 130 (FIG. 4) of the intermediate template structure 128 (i.e., perpendicular to the direction of the parallel spacers 122). For example, each of the additional parallel spacers 148 may have a width W₄, thickness T₅, and length (not shown) substantially the same as the width W₂, the thickness T₃, and the length (not shown) of the parallel spacers 122, respectively. Accordingly, the width W₄ of each of the additional parallel spacers 148 may be within a range of from about 20 percent to about 40 percent of a target pitch between adjacent openings of the rectilinear array of openings to be formed using the template structure, such as from about 20 percent to about 30 percent of the target pitch. In further embodiments, at least one of the thickness T₅ and the length of the each of the additional parallel spacers 148 may be different than at least one of the thickness T₃ and the length of the parallel spacers 122. In addition, the additional parallel spacers 148 may be regularly spaced by a distance D₄ (i.e., equal to the width W₃ of each of the additional parallel photoresist lines 142), that is substantially the same as the distance D₂ between each of the parallel spacers 122. Accordingly, the distance D₄ between adjacent additional parallel spacers 148 may be within a range of from about 180 percent to about 160 percent of the target pitch between adjacent openings of the rectilinear array of openings to be formed using the template structure, such as from about 180 percent to about 170 percent of the target pitch. A pitch P₄ between centerlines C₄ of adjacent additional parallel spacers of the another patterned spacer material 146 may be substantially the same as the pitch P₂ between the centerlines C₂ of the adjacent parallel spacers of the patterned spacer material 120 (i.e., equal to about half of the pitch P₃ between centerlines C₃ of adjacent additional parallel photoresist lines of the additional parallel photoresist lines 142). Accordingly, the pitch P₄ between adjacent additional parallel spacers of the another patterned spacer material 146 may be equal to about two times (2×) the target pitch between adjacent openings of the rectilinear array of openings to be formed using the template structure.

By way of non-limiting example, if a target pitch between adjacent openings of the rectilinear array of openings to be formed is about 30 nm, the width W₄ of each of the additional parallel spacers 148 may be within a range of from about 6 nm to about 12 nm, the distance D₄ between adjacent additional parallel spacers of the another patterned spacer material 146 may be within a range of from about 54 nm and about 48 nm, and the pitch P₄ between centerlines C₄ of adjacent additional parallel spacers of the another patterned spacer material 146 may be about 60 nm. In some embodiments, the width W₄ of each of the additional parallel spacers 148 is about 10 nm, the distance D₄ between adjacent additional parallel spacers of the another patterned spacer material 146 is about 50 nm, and the pitch P₄ between adjacent parallel spacers of the another patterned spacer material 146 is about 60 nm. The another patterned spacer material 146 may be formed using processes substantially similar to those previously described with respect to forming the patterned spacer material 120.

Referring to FIGS. 7A and 7B, the first pattern 152 defined by the another patterned spacer material 146 (FIG. 6) may be transferred or extended into the intermediate template structure 128 (FIG. 4) to form a template structure 154. The template structure 154 may include parallel features 130′ (described in more detail below), additional parallel features 156, and elevated pillars 158. The parallel features 130′ may intersect with the additional parallel features 156 to at least partially define wells 160. The elevated pillars 158 may protrude from the locations where the parallel features 130 and the additional parallel features 156 intersect. A height H₃ of the elevated pillars 158 may be equal to the difference between a height H₄ of each of the parallel features 130 and the additional parallel features 156 and the thickness T₁ of the template material 106 (FIGS. 1 and 2). In some embodiments, the height H₃ of the elevated pillars 158 is about 40 nm.

The parallel features 130′ may be substantially similar (e.g., in terms of dimensions and spacing) to the parallel features 130 of the intermediate template structure 128 previously described with reference to FIG. 4, except that, as a result of extending the second pattern 152 into the intermediate template structure 128, the parallel features 130′ may be formed from what used to be portions of the base 132 underlying the parallel features 130. Thus, as shown in FIG. 7B, the parallel features 130′ of the template structure 154 may have substantially the same width W₂, length (not numbered), and pitch P₂ as the parallel features 130 of the intermediate template structure 128 (FIG. 4).

The additional parallel features 156 may have substantially the same width W₄, length (not shown), and pitch P₄ as each of the additional parallel spacers 148 (FIG. 6). The additional parallel features 156 may also have substantially the same dimensions and spacing as the parallel features 130′, except oriented in a direction substantially perpendicular to that of the parallel features 130′. For example, referring to FIG. 7B, the width W₄ of each of the additional parallel features 156 may be substantially the same as the width W₂ of each of the parallel features 130′, the distance D₄ between adjacent additional parallel features of the additional parallel features 156 may be substantially the same as the distance D₂ between adjacent parallel features of the parallel features 130′, and the pitch P₄ between centerlines C₄ of adjacent additional parallel features of the additional parallel features 156 may be substantially the same as the pitch P₂ between centerlines C₂ of adjacent parallel features of the parallel features 130. Thus, the template structure 154 may include intersecting parallel features (i.e., the parallel features 130′, and the additional parallel features 156) defining substantially rectangular (e.g., square) wells. In addition, as illustrated in FIG. 7A, each of the additional parallel features 156 and the parallel features 130′ may have substantially the same height H₃.

Since the parallel features 130′ and the additional parallel features 156 have substantially the same dimensions and spacing as the parallel spacers 122 and the additional parallel spacers 148, the width W₂ of each of the parallel features 130′ and the width W₄ of each of the additional parallel features 156 may both be within a range of from about 20 percent to about 40 percent of a target pitch between adjacent openings of a rectilinear array of openings to be formed using the template structure 154, such as from about 20 percent to about 30 percent of the target pitch. In addition the distance D₂ between each of the parallel spacers 122 and the distance D₄ between of the additional parallel spacers 148 may be within a range of from about 180 percent to about 160 percent of the target pitch between adjacent openings of the rectilinear array of openings to be formed using the template structure 154, such as from about 180 percent to about 170 percent of the target pitch. Further, the pitch P₂ between centerlines C₂ of adjacent parallel features of the parallel features 130′ and the pitch P₄ between centerlines C₄ of adjacent additional parallel features of the additional parallel features 156 may both be about two times (2×) the target pitch between adjacent openings of the rectilinear array of openings. Still further, the height H₃ of each of the parallel features 130′ and the additional parallel features 156 may be within a range of from about one-half (½) the target pitch between adjacent openings of the rectilinear array of openings and about three times (3×) the target pitch between adjacent openings of the rectilinear array of openings, such as from about one times (1×) the target pitch and about two times (2×) the target pitch.

By way of non-limiting example, if a target pitch between adjacent openings of the rectilinear array of openings to be formed is about 30 nm, the width W₂ of each of the parallel features 130′ and the width W₄ of each of the additional parallel features 156 may be within a range of from about 6 nm to about 12 nm, the distance D₂ between adjacent parallel features of the parallel features 130′ and the distance D₄ between adjacent additional parallel features of the additional parallel features 156 may both be within a range of from about 54 nm and about 48 nm, the pitch P₂ between centerlines C₂ of adjacent parallel features of the parallel features 130′ and the pitch P₄ between centerlines C₄ of adjacent additional parallel features of the additional parallel features 156 may both be about 60 nm, and the height H₃ of each of the parallel features 130′ and the additional parallel features 156 may be within a range of from about is about 15 nm to about 90 nm. In some embodiments, the width W₂ of each of the parallel features 130′ and the width W₄ of each of the additional parallel features 156 are both about 10 nm, the distance D₂ between adjacent parallel features of the parallel features 130′ and the distance D₄ between adjacent additional parallel features of the additional parallel features 156 are both about 50 nm, the pitch P₂ between centerlines C₂ of adjacent parallel features of the parallel features 130′ and the pitch P₄ between centerlines C₄ of adjacent additional parallel features of the additional parallel features 156 are both about 60 nm, and the height H₃ of each of the parallel features 130′ and the additional parallel features 156 is about 35 nm.

As depicted in FIGS. 7A and 7B, the parallel features 130′ and the additional parallel features 156 may define sidewalls 162 of each the wells 160, and the substrate masking material 104 may define a floor 164 of each of the wells 160. Thus, if the parallel features 130′ and the additional parallel features 156 have substantially the same dimensions and spacing, each of the wells 160 may have substantially the same shape (e.g., substantially rectangular, such as substantially square), dimensions, and spacing. In some embodiments, each of the wells 160 has a square lateral cross-sectional shape, a lateral cross-sectional area of about 2500 nm², a height of about 35 nm, and is spaced apart from an adjacent well by about 10 nm.

Referring collectively to FIGS. 4, 6, and 7A, to form the template structure 154, the additional parallel spacers 148 of the another patterned spacer material 146 may be used as a mask for at least one etching process (e.g., an anisotropic etching process) to remove unmasked portions (e.g., portions not underlying the additional parallel spacers 148) of each of the additional template masking materials 134 and the intermediate template structure 128 (FIG. 4). The unmasked portions of the additional template masking materials 134 may be completely removed, and the unmasked portions of the intermediate template structure 128 may be partially removed. The etching process may, for example, uniformly remove unmasked portions of the intermediate template structure 128 to completely remove unmasked portions of the base 132 not underlying the parallel features 130 (FIG. 4) and to transfer the dimensions of the parallel features 130 into the unmasked portions of the base 132 underlying the parallel features 130 (e.g., to form the parallel features 130′ of the template structure 154). In further embodiments, depending on the conditions (e.g., time, chemistries, etc.) of the etching process, the height H₁ of the parallel features 130 of the intermediate template structure 128 may be different than (e.g., larger than) the height H₃ of the parallel features 130′ of the template structure 154. Remaining portions of the additional parallel spacers 148 and the additional template masking materials 134 may then be selectively removed relative to the template structure 154.

Referring to FIGS. 8A and 8B, a neutral wetting material 166 may be formed over the substrate masking material 104 defining the floor 164 of each of the wells 160. The neutral wetting material 166 may be a material that has exhibits equal affinity for different polymer blocks (and any corresponding homopolymers, if present) of a block copolymer material to be deposited in the wells 160. Thus, the neutral wetting material 166 may not be preferential (e.g., selective) to any polymer block (or homopolymer, if present) of a block copolymer material. The neutral wetting material 166 may, for example, be a neutral wetting carbon material, or a neutral wetting polymer. As a non-limiting example, if the block copolymer material to be deposited in the wells 160 is PS-b-PMMA, the neutral wetting material 166 may be a random PS:PMMA copolymer material (P(S-r-MMA)), a benzocyclobutene (BCP)- or azidomethylstyrene (AMS)-functionalized random copolymer of styrene and methyl methacrylate (e.g., P(S-r-MMA-r-BCP)), a hydroxyl functionalized random copolymer of styrene and methyl methacrylate (e.g., a 2-hydroxyethyl methacrylate (HEMA) functionalized random copolymer of styrene and methyl methacrylate (P(S-r-MMA-r-HEMA))), or a neutral wetting carbon material. In some embodiments, the neutral wetting material 166 is a neutral wetting carbon material. The neutral wetting material 166 may partially fill each of the wells 160. The neutral wetting material 166 may be formed at any suitable thickness facilitating the formation of the self-assembled block copolymer material, such as a thickness within a range of from about 5 nm to about 10 nm.

The neutral wetting material 166 may be formed using conventional processes (e.g., a PVD process, a CVD process, an ALD process, or a spin-coating process), which are not described in detail herein. By way of non-limiting example, if the neutral wetting material 166 is a neutral wetting carbon material, the neutral wetting carbon material may be deposited in the wells 160 by a CVD process. As another non-limiting example, if the neutral wetting material 166 is a neutral wetting random copolymer material, the neutral wetting random copolymer material may be spin-coated into the wells 160 and cross-linked (e.g., by way of at least one of thermal-processing and photo-processing). After forming the neutral wetting material 166 on the floor 164 of the wells 160, portions of the neutral wetting material 166 present on surfaces of the template structure 154 (e.g., surfaces of the parallel features 130′, the additional parallel features 156, and the elevated pillars 158 not proximate the substrate masking material 104) may be removed.

In additional embodiments, the neutral wetting material 166 may be formed on the substrate masking material 104 prior to forming the template structure 154. For example, the neutral wetting material 166 may be formed between the substrate masking material 104 and the template material 106 (FIG. 1), and then the template structure 154 may be formed as previously described with reference to FIGS. 1 through 7B (i.e., such that the template structure 154 is formed over the neutral wetting material 166, and such that the neutral wetting material 166 defines the floor 164 of each of the wells 160).

Referring next to FIGS. 9A and 9B, a block copolymer material 168 may be formed (e.g., deposited) in each of the wells 160. As used herein, the term “block copolymer material” means and includes a material including at least one block copolymer. In turn, as used herein, the term “block copolymer” means and includes a polymer including two or more polymer blocks covalently bound to one or more polymer blocks of unlike type. The block copolymer material may also include at least one homopolymer of the same polymer type as a polymer block of the block copolymer included therein. As used herein, the term “homopolymer” means and include a polymer including a single type of repeat unit (e.g., a single repeating monomer). For example, the block copolymer material 168 may be a self-assembling (SA) block copolymer (e.g., an SA diblock copolymer, an SA triblock copolymer, etc.), or may be a blend of an SA block copolymer and at least one homopolymer of the same polymer type as a polymer block of the SA block copolymer. Suitable SA block copolymers may include, but are not limited to, PS-b-PMMA, PS-b-PDMS, polystyrene-block-polyvinylpyridine (PS-b-PVP), polystyrene-block-polyisoprene (PS-b-PI), polystyrene-block-polybutadiene (PS-b-PB), polystyrene-block-polylactide (PS-b-PA), polyethyleneoxide-block-polyisoprene (PEO-b-PI), polyethyleneoxide-block-polybutadiene (PEO-b-PB), polyethyleneoxide-block-polymethylmethacrylate (PEO-b-PMMA), polyethyleneoxide-block-polystyrene (PEO-b-PS), polybutadiene-block-polyvinylpyridine (PB-b-PVP), polyisoprene-block-polymethylmethacrylate (PI-b-PMMA). In some embodiments, the block copolymer material 168 is PS-b-PMMA. In additional embodiments, the block copolymer material 168 is PS-b-PDMS.

The block copolymer material 168 may have an SA block copolymer chain length and volumetric ratio of constituent polymers (i.e., polymer blocks of the SA block copolymer, and, if present, any homopolymers) facilitating the formation of a rectangular (e.g., square) array of cylindrical domains of a first polymer within a matrix domain of a second polymer in each of the wells 160, as described in further detail below. For example, if the block copolymer material 168 is an SA diblock copolymer, a first polymer block to be self-assembled into the cylindrical domains may constitute from about 20 percent to about 40 percent of the total volume of the SA diblock copolymer, and a second polymer block to be self-assembled into the matrix domain may constitute a remaining percentage of the total volume of the SA diblock copolymer (e.g., from about 80 percent to about 60 percent of the total volume of the SA diblock copolymer). If the block copolymer material 168 is a blend of an SA block copolymer and at least one homopolymer, the at least one homopolymer may constitute from about 0.1 percent to about 40 percent of the total volume of the blend. In some embodiments, the block copolymer material 168 is a PS-b-PMMA copolymer including about 30 percent by volume PS and about 70 percent by volume PMMA. In additional embodiments, the block copolymer material 168 is a PS-b-PDMS diblock copolymer including about 30 percent by volume PS and about 70 percent by volume PDMS.

The block copolymer material 168 may substantially fill a remaining portion of each of the wells 160 (i.e., a portion of each of the wells 160 remaining after the formation of the neutral wetting material 166 therein). The sidewalls 162 of the wells 160 may be preferential wetting to one of the polymer blocks of the block copolymer material 168. In addition, the block copolymer material 168 may be substantially contained within the wells 160 (i.e., less than or equal to a monolayer of the block copolymer material 168 may be located outside of the wells 160, such as on the surfaces of the parallel features 130′, the additional parallel features 156, and the elevated pillars 158 outside of the wells 160). In some embodiments, the block copolymer material 168 has a thickness within a range of about 25 nm to about 30 nm and is substantially contained in the wells 160.

The block copolymer material 168 may be formed in each of the wells 160 using conventional processes (e.g., spin-coating, knife-coating, etc.), which are not described in detail herein. By way of non-limiting example, the block copolymer material 168 may be deposited into each of the wells 160 by spin-coating from a dilute solution of the block copolymer material 168 in an organic solvent (e.g., dichloroethane, toluene, etc.). The deposition process may be controlled so that capillary forces pull excess of the block copolymer material 168 (e.g., block copolymer material 168 deposited outside of the wells 160) greater than a monolayer into the wells 160.

Referring to FIGS. 10A and 10B, the block copolymer material 168 (FIGS. 9A and 9B) may be processed (e.g., annealed) to form a self-assembled block copolymer material 170 including a rectilinear array 172 of cylindrical domains 176 of a first polymer within a matrix domain 174 of a second polymer. The first polymer may correspond to a minority polymer of the block copolymer material 168 (e.g., a polymer, including a polymer block of an SA block copolymer and any corresponding homopolymer, present in a relatively lower amount), and the second polymer may correspond to a majority polymer of the block copolymer material 168 (e.g., another polymer, including another polymer block of an SA block copolymer and any corresponding homopolymer, present in a relatively greater amount). The sidewalls 162 of the wells 160 may be preferential wetting to the majority polymer of the block copolymer material 168. For example, if the block copolymer material 168 is an SA block copolymer (e.g., an SA diblock copolymer), the first polymer may correspond to a minority polymer block of the SA block copolymer and the second polymer may correspond to a majority polymer block of the SA block copolymer. In some embodiments, the cylindrical domains 176 are formed of and include PS, and the matrix domain 174 is formed of and includes PMMA. In additional embodiments, the cylindrical domains 176 are formed of and include PS, and the matrix domain 174 is formed of and includes PDMS.

As shown in FIG. 10B, the rectilinear array of cylindrical domains 172 may include rows of cylindrical domains 176 of the first polymer extending in an X direction and columns of the cylindrical domains 176 of the first polymer extending in a Y direction. The X direction may be substantially perpendicular to the Y direction. Each of the cylindrical domains 176 of the first polymer may have substantially the same width W₅ (i.e., diameter) and height H₅, and may be oriented perpendicular (i.e., surface normal) to the substrate 102. In addition, within each row and each column, the cylindrical domains 176 of the first polymer may be substantially aligned and regularly spaced by a distance D₅. A pitch P₅ between centers C₅ of adjacent cylindrical domains (e.g., adjacent cylindrical domains of a particular row or a particular column) of the rectilinear array of cylindrical domains 172 may be substantially uniform throughout the self-assembled block copolymer material 170.

By way of non-limiting example, the width W₅ of each of the cylindrical domains 176 of the first polymer may be equal to about one-fourth (¼) of the pitch (e.g., the pitch P₂, and the pitch P₄) between centerlines (e.g., the centerlines C₂, and the centerlines C₄) of adjacent features (e.g., adjacent parallel features of the parallel features 130′, and adjacent additional parallel features of the additional parallel features 156) of the template structure 154. In addition, the height H₅ of each of the cylindrical domains 176 of the first polymer may be equal to the height of the block copolymer material 168 (FIGS. 9A and 9B). Furthermore, the pitch P₅ between centers C₅ of adjacent cylindrical domains may be equal to about one-half (½) of the pitch (e.g., the pitch P₂, and the pitch P₄) between centerlines (e.g., the centerlines C₂, and the centerlines P₄) of adjacent parallel features (e.g., adjacent parallel features of the parallel features 130′, and adjacent additional parallel features of the additional parallel features 156) of the template structure 154. In some embodiments, the width W₅ of each of the cylindrical domains 176 is about 15 nm, the height H₅ of the cylindrical domains 176 is within a range of from about 25 nm to about 30 nm, and the pitch P₅ between centers C₅ of adjacent cylindrical domains of the cylindrical domains 176 is about 30 nm.

As illustrated in FIG. 10B, the rectilinear array 172 of cylindrical domains 176 of the first polymer may be considered an aggregate of rectangular (e.g., square) arrays (not numbered) of the cylindrical domains 176 of the first polymer contained within the wells 160. Namely, within each of the wells 160, the dimensions and preferential wetting characteristics of the sidewalls 162 (i.e., as defined by parallel features 130′ and additional parallel features 156 of the template structure 154) in combination with the characteristics of the neutral wetting material 166, facilitates the formation of a rectangular array of the cylindrical domains 176 of the first polymer within the matrix domain 174 of the second polymer. Each rectangular array includes four of the cylindrical domains 176 of the first polymer having the dimensions and spacing previously described (e.g., width W₅, height H₅, and pitch P₅) in rectangular (e.g., square) registration. In turn, the dimensions and spacing of each of the parallel features 130′ and the additional parallel features 156 of the template structure 154 enables adjacent cylindrical domains 176 of adjacent rectangular arrays (i.e., in adjacent wells) to have the same alignment, dimensions, and spacing, resulting in the rectilinear array 172 of cylindrical domains 176.

The self-assembled block copolymer material 170 may be formed using a annealing process. For example, the block copolymer material 168 may be thermally annealed at a temperature above the glass transition temperature of the polymer blocks and homopolymers (if any) of the block copolymer material 168 to effectuate separation and self-assembly according to the wetting characteristics of the wells 160 (e.g., the preferential wetting characteristics of the sidewalls 162, and the neutral wetting characteristics of the neutral wetting material 166 on the floor 164). As another example, the block copolymer material 168 may be solvent annealed by swelling the polymer blocks and homopolymers (if any) of the block copolymer material 168 with a solvent and then evaporating the solvent. In some embodiments, such as where the block copolymer material 168 is a PS-b-PMMA copolymer, the block copolymer material 168 is annealed at a temperature within a range of from about 180° C. to about 250° C. in a vacuum oven or under an inert atmosphere for a period of time within a range of from about 2 minutes to about 24 hours to form the self-assembled block copolymer material 170.

Referring next to FIGS. 11A and 11B, the cylindrical domains 176 (FIGS. 10A and 10B) of the first polymer may be selectively removed to form a patterned polymer material 178 including the matrix domain 174 of the second polymer surrounding cylindrical openings 180. The cylindrical openings 180 have substantially the same dimensions (e.g., width W₅, and height H₅), spacing (e.g., distance D₅, and pitch P₅), and alignment as the cylindrical domains 176 of the first polymer. The patterned polymer material 178 may thus define a rectilinear pattern 182 of cylindrical openings 180 (i.e., derived from and having substantially the same dimensions and spacing as the rectilinear array of cylindrical domains 172 of the first polymer) to be transferred to the substrate 102, as described in further detail below.

The selective removal of the cylindrical domains 176 of the first polymer to form the patterned polymer material 178 may be performed using conventional processes, which are not described in detail herein. By way of non-limiting example, the cylindrical domains 176 of the first polymer may be removed using at least one of an oxygen plasma process and a chemical dissolution process (e.g., a process including irradiating the cylindrical domains 176 of the first polymer, ultrasonicating the self-assembled block copolymer material 170 in acetic acid, ultrasonicating the self-assembled block copolymer material 170 in deionized water, and rinsing the self-assembled block copolymer material 170 to remove the cylindrical domains 176 of the first polymer).

Referring next to FIGS. 12A and 12B, the rectilinear pattern 182 of cylindrical openings 180 defined by the patterned polymer material 178 may be transferred or extended into the substrate 102 (FIGS. 1A and 11B) to form a patterned substrate 184 including a rectilinear array 186 of openings 188. The rectilinear array 186 may include rows of openings 188 extending in the X direction and columns of the openings 188 extending in the Y direction. The openings 188 may extend partially into the patterned substrate 184, or may extend completely through the patterned substrate 184. The openings 188 may have substantially the same width W₅ as the cylindrical openings 180 of the patterned polymer material 178 (i.e., the same width W₅ as the cylindrical domains 176 of the self-assembled block copolymer material 170). In addition, within each row and each column, the openings 188 may be substantially aligned and may have the same pitch P₅ as the cylindrical openings 180 of the patterned polymer material 178 (i.e., the same pitch P₅ as the cylindrical domains 176 of the self-assembled block copolymer material 170). In some embodiments, each of the openings 188 extends partially into the patterned substrate 184, the width W₅ of each of the openings 188 is about 15 nm, and the pitch P₅ between adjacent openings 188 is about 30 nm.

To form the patterned substrate 184, the matrix domain 174 of the patterned polymer material 178 may be used as a mask for at least one etching process (e.g., an anisotropic etching process, such as an reactive ion etching process) to substantially remove unmasked portions (e.g., portions not underlying the matrix domain 174) of each of the substrate masking material 104 and the substrate 102. The unmasked portions of the substrate masking material 104 may be completely removed, and the unmasked portions of the substrate 102 may be at least partially removed (i.e., may be partially removed, or may be completely removed). The etching process may, for example, extend the rectilinear pattern 182 of openings 180 partially through the substrate 102 to form the rectilinear array 186 of openings 188 of the patterned substrate 184.

Accordingly, a method of forming a rectilinear array of openings in a substrate may comprise forming a template structure comprising a plurality of parallel features and a plurality of additional parallel features perpendicularly intersecting the plurality of additional parallel features of the plurality over a substrate to define wells, each of the plurality of parallel features having substantially the same dimensions and relative spacing as each of the plurality of additional parallel features. A block copolymer material may be formed in each of the wells. The block copolymer material may be processed to form a patterned polymer material defining a pattern of openings. The pattern of openings may be transferred to the substrate to form an array of openings in the substrate.

In addition, a method of forming a semiconductor device structure may comprise forming a template structure comprising intersecting features defining substantially rectangular wells over a substrate, each of the intersecting features having substantially the same dimensions and being preferential wetting to a polymer block of a self-assembling block copolymer. A neutral wetting material may be formed over a floor of each of the substantially rectangular wells. A block copolymer material comprising the self-assembling block copolymer may be formed over the neutral wetting material. The block copolymer material may be self-assembled to form an array of cylindrical domains of a first polymer within a matrix domain of a second polymer, the array of cylindrical domains of the first polymer exhibiting uniform pitch between substantially all adjacent cylindrical domains of the first polymer. The cylindrical domains of the first polymer may be selectively removed to define a pattern of cylindrical openings in the matrix domain of the second polymer. The pattern of cylindrical openings may be transferred to the substrate.

Following the formation of the patterned substrate 184, remaining portions of the template structure 154 (e.g., the parallel features 130′, the additional parallel features 156, and the elevated pillars 158), patterned polymer material 178 (e.g., the matrix domain 174), and the substrate masking material 104 may be removed, as depicted in FIGS. 13A and 13B. These materials may be removed using conventional processes, such as conventional etching processes, which are not described in detail herein. The semiconductor device structure 100 including the patterned substrate 184 may then be subjected to additional processing, as desired. For example, the openings 188 in the substrate 102 may be at least partially filled with a material, such as a conductive material, to form contacts (e.g., bond pads). By utilizing the methods of the disclosure, the contacts may be closely packed and may have a uniform pitch between adjacent contacts.

Accordingly, a semiconductor device structure of the disclosure may comprise a substrate defining a rectilinear array of openings, each opening of the rectilinear array of openings having substantially the same width of less than or equal to about 25 nm, and adjacent openings of the rectilinear array of openings having substantially the same pitch of less than or equal to about 50 nm.

The methods of the disclosure provide an effective and reliable way to control the dimensions and spacing of the rectilinear array of openings 186 of the patterned substrate 184. The methods facilitate simple and cost-effective formation of very small openings 188 (e.g., critical dimensions of less than or equal to about 30 nm) that are closely packed (e.g., a pitch of less than or equal to about 50 nm) and are substantially aligned in multiple directions (e.g., in the X and Y directions). The methods of the disclosure advantageously facilitate improved device performance, lower cost, increased miniaturization of components, and greater packaging density as compared to conventional methods of forming a contact array for a semiconductor device structure (e.g., a DRAM device structure).

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure as defined by the following appended claims and their legal equivalents. 

1. A semiconductor device structure, comprising a substrate defining a rectilinear array of openings, each opening of the rectilinear array of openings having substantially the same width of less than or equal to about 25 nm, and adjacent openings of the rectilinear array of openings having substantially the same pitch of less than or equal to about 50 nm.
 2. The semiconductor device structure of claim 1, wherein the width of each opening of the rectilinear array of openings is less than or equal to about 15 nm.
 3. The semiconductor device structure of claim 1, wherein the pitch between the adjacent openings of the rectilinear array of openings is than or equal to about 30 nm.
 4. The semiconductor device structure of claim 1, wherein each opening of the rectilinear array of openings comprises a cylindrical opening.
 5. The semiconductor device structure of claim 1, wherein the rectilinear array of openings extends partially into the substrate.
 6. The semiconductor device structure of claim 1, wherein the rectilinear array of openings extends completely through the substrate.
 7. The semiconductor device structure of claim 1, wherein the rectilinear array of openings comprises rows of openings intersecting columns of openings at about a ninety degree angle.
 8. The semiconductor device structure of claim 1, wherein each opening the rectilinear array of openings is at least partially filled with a material.
 9. The semiconductor device structure of claim 8, wherein the material comprises a conductive material.
 10. The semiconductor device structure of claim 1, wherein the substrate comprises a semiconductive material.
 11. A semiconductor device structure, comprising: a substrate exhibiting an array of cylindrical openings at least partially extending therethrough, the array of cylindrical openings comprising: at least one row of cylindrical openings, adjacent cylindrical openings of the at least one row of cylindrical openings exhibiting a pitch of less than or equal to about 50 nm; and at least one column of cylindrical openings intersecting the at least one row of cylindrical opening at about a ninety degree angle, adjacent cylindrical openings of the at least one column of cylindrical openings exhibiting a pitch of less than or equal to about 50 nm.
 12. The semiconductor device structure of claim 11, wherein each cylindrical opening of the at least one row of cylindrical openings is substantially uniformly spaced from each other cylindrical opening of the at least one row of cylindrical openings adjacent thereto.
 13. The semiconductor device structure of claim 11, wherein each cylindrical openings of the at least one column of cylindrical openings is substantially uniformly spaced from each other cylindrical opening of the at least one column of cylindrical openings adjacent thereto.
 14. The semiconductor device structure of claim 11, wherein a first distance between the adjacent cylindrical openings of the at least one row of cylindrical openings is substantially the same as a second distance between the adjacent cylindrical openings of the at least one column of cylindrical openings.
 15. The semiconductor device structure of claim 11, wherein each cylindrical opening of the at least one row of cylindrical openings exhibits a diameter of less than or equal to about 30 nm.
 16. The semiconductor device structure of claim 11, wherein each cylindrical opening of the at least one column of cylindrical openings exhibits a diameter of less than or equal to about 30 nm.
 17. The semiconductor device structure of claim 11, wherein each cylindrical opening of the at least one row of cylindrical openings and each cylindrical opening of the at least one column of cylindrical openings exhibits substantially the same diameter of less than or equal to about 15 nm.
 18. A semiconductor device, comprising: a substrate exhibiting a rectilinear array of openings, the rectilinear array of openings formed by a method comprising: forming a template structure comprising parallel features and additional parallel features perpendicularly intersecting the additional parallel features over the substrate to define wells, each of the parallel features exhibiting substantially the same dimensions and relative spacing as each of the additional parallel features; forming a block copolymer material in the wells; processing the block copolymer material to form a patterned polymer material exhibiting a pattern of openings; and transferring the pattern of openings to the substrate.
 19. The semiconductor device of claim 18, wherein adjacent openings of the rectilinear array of openings are substantially uniformly spaced by less than or equal to about 30 nm.
 20. The semiconductor device of claim 19, wherein each opening of the rectilinear array of openings exhibits substantially the same width of less than or equal to about 15 nm. 